Using constraints in design verification

Details Using constraints in design verification Using constraints in design verification

2008-06-30

2010-12-21

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07856609

ABSTRACT:
A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.

REFERENCES:
patent: 2004/0123254 (2004-06-01), Geist et al.
patent: 2004/0230407 (2004-11-01), Gupta et al.
“Cutpoints for Formal Equivalence Verification of Embedded Software”, by Xiaushan Feng and Alan J. Hu, EMSOFT'05 , Sep. 19-22, 2005 @ ACM.

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