Use of non-lithographic shrink techniques for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

10838830

ABSTRACT:
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.

REFERENCES:
patent: 6516528 (2003-02-01), Choo et al.

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