Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-02
2007-01-02
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10838830
ABSTRACT:
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.
REFERENCES:
patent: 6516528 (2003-02-01), Choo et al.
Amblard Gilles
Phan Khoi A.
Singh Bhanwar
Advanced Micro Devices , Inc.
Amin Turocy & Calvin LLP
Dinh Paul
LandOfFree
Use of non-lithographic shrink techniques for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of non-lithographic shrink techniques for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of non-lithographic shrink techniques for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3721564