Using constrained scan cells to test integrated circuits

Details Using constrained scan cells to test integrated circuits Using constrained scan cells to test integrated circuits

2007-11-13

2007-11-13

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S025000, C714S726000, C714S738000

Reexamination Certificate

active

10961760

ABSTRACT:
Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.

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