Local word line decoder for memory with 2 1/2 MOS devices
Local word line decoder for memory with 2 MOS devices
Local word line phase driver
Local word line phase driver
Local write driver circuit for an integrated circuit device...
Localized ATD summation for a memory
Localized direct sense architecture
Localized MRAM data line and method of operation
Location-specific NAND (LS NAND) memory technology and cells
Location-specific NAND (LS NAND) memory technology and cells
Lock-out device and semiconductor integrated circuit device...
Lockout circuit and method for preventing metastability during t
Lockout registers
Logged-based flash memory system and logged-based method for...
Logic and memory circuit with reduced input-to-output signal pro
Logic and memory device integration
Logic array having improved speed characteristics
Logic cell array using CMOS EPROM cells having reduced chip surf
Logic cell protected against random events
Logic circuit