Lockout registers

Details Lockout registers Lockout registers

1988-04-01

1989-04-25

Fears, Terrell W.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365189, 364200, G11C 1500

Patent

active

048254126

ABSTRACT:
A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location. The backmap invalidates all copies of the data in the storage cache after every reference to data in the storage cache using an address in the lockout register.

REFERENCES:
patent: 4559618 (1985-12-01), Houseman et al.

Affiliated with

Also associated with

Rating

Lockout registers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Lockout registers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lockout registers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1201003