Local word line decoder for memory with 2 MOS devices

Details Local word line decoder for memory with 2 MOS devices Local word line decoder for memory with 2 MOS devices

1997-10-06

1999-02-02

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, 36523008, G11C 800, G11C 1604

Patent

active

058674454

ABSTRACT:
A method and a circuit are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and by reducing the number of inputs to the decoder from three to two. The reduction in inputs is made possible by the method of applying to one of the inputs, when low, a voltage signal v.sub.b which is at least one threshold lower than the voltage signal to the other input, when low. This voltage v.sub.b can be derived from the p-substrate bias voltage.

REFERENCES:
patent: 5446698 (1995-08-01), McClure
patent: 5555529 (1996-09-01), Hose, Jr. et al.
patent: 5587960 (1996-12-01), Ferris
patent: 5608678 (1997-03-01), Lysinger
patent: 5612918 (1997-03-01), McClure
patent: 5648933 (1997-07-01), Slemmer

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