Logic array having improved speed characteristics

Details Logic array having improved speed characteristics Logic array having improved speed characteristics

1978-11-29

1980-06-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

307205, G11C 1140, G11C 1300

Patent

active

042076161

ABSTRACT:
An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of similarly improved logic arrays. The ROM includes parallel rows of conductors oriented normal to parallel doped regions which form column conductors. The ROM is implemented with field-effect transistors and comprises two decoder fields and a data field. The transistors of the decoder fields serve to define open circuits between adjacent column conductors in accordance with binary input signals applied to the decoder fields. In the illustrative ROM, a first column conductor is connected to a return terminal of a power supply and a second column conductor is connected to a "pull-up" circuit. The illustrative circuit provides for the connection of power supply return connections to both ends of the one column conductor and provides for the connection of pull-up circuits to both ends of the second column conductor. The row conductors are connected to gates of transistors in both the data and the decoder fields and a low impedance path from the pull-up circuits to the power supply return is established in response to signals on the row conductors.

REFERENCES:
patent: 3982138 (1976-09-01), Luisi et al.
patent: 4025799 (1977-05-01), Cox et al.

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