Loadless SRAM

Local bank write buffers for accelerating a phase-change memory

Local interconnect structure and process for six-transistor SRAM

Local probe of magnetic properties

Localized MRAM data line and method of operation

Logic cell protected against random events

Logic circuit using resonant-tunneling transistor

Logic circuit with a test capability

Logic-in-memory circuit using magnetoresistive element

Logical operation circuit and logical operation method

Loop organized serial-parallel-serial memory storage system

Low AC power SRAM architecture

Low aspect ratio magnetoresistive tunneling junction

Low charge consumption memory

Low cost mixed memory integration with substantially coplanar ga

Low cost three-dimensional memory array

Low cross-talk electrically programmable resistance cross...

Low current switching magnetic tunnel junction design for...

Low equalized sense-amp for twin cell DRAMs

Low fatigue sensing method and circuit for ferroelectric...