Low charge consumption memory

Details Low charge consumption memory Low charge consumption memory

1994-03-23

1995-05-09

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365203, 365210, G11C 700

Patent

active

054146569

ABSTRACT:
A dynamic random access memory is improved by a storage node precharge circuit so as to obtain both high stored voltage level and low charge consumption from a power supply. High voltage levels are written via the precharge circuit. Subsequently, low voltage levels are written via the access transistors and bit lines. As a result, the magnitude of the storage node voltage swing is independent of the magnitude of the bit line voltage swing. A given memory design may therefore be optimized independently for high stored voltage level and low bit line charge consumption.

REFERENCES:
patent: 4203159 (1980-05-01), Wanless
patent: 4593382 (1986-06-01), Fujishima et al.
patent: 4896294 (1990-01-01), Shimizu et al.
patent: 4935896 (1990-06-01), Matsumura et al.
Kazuyasu Fujishima et al., IEEE J. Solid State Circuits, vol. SC-17, No. 5, Oct. 1982, "A Storage Mode Boosted RAM with Word Line Delay Compensation," pp. 872-876.
Masahazu Aoki et al., IEEE J. Solid State Circuits, vol. 24, No. 5, Oct. 1989, "A 1.5V DRAM for Battery Based Applications," pp. 1206-1212.

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