Low cost three-dimensional memory array

Details Low cost three-dimensional memory array Low cost three-dimensional memory array

2001-08-13

2003-02-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Three-dimensional magnetic array

C365S225700, C365S113000, C365S105000

Reexamination Certificate

active

06515888

ABSTRACT:

BACKGROUND
This invention relates to three-dimensional memory arrays of the type that include multiple vertically-stacked layers of memory cells, and in particular to such memory arrays that are particularly low in manufacturing cost.
The marketplace is demanding memory chips containing an ever-larger number of storage bits, at an ever-lower cost per bit. It is extremely desirable to provide a high-capacity memory at a very low cost, to serve this expanding market.
Conventional memory design assumes that high-speed read access is an important goal. The basic memory cell is conventionally designed to provide a relatively large read current, ensuring a relatively fast read access. Unfortunately, to produce these relatively large read currents, relatively large switching devices are needed, and the large devices give rise to relatively large memory cells. Large memory cells cause the memory chip area to be large, which means the memory chip cost will be high (since the cost increases as the area grows).
For example, as described by P. Cappalletti, et al. (
Flash Memories,
Kluwer Academic Publishers, Norwell, Mass., USA, Copyright 1999, ISBN 0-7923-8487-3), the typical read current of a conventional, two-dimensional flash memory cell array is 100 microamperes (page 42), and the worst-case read current in such an array could range from 1 to 5 microamperes (page 308).
Similarly, S. Kawashima, et al. (“A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAMS,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998, pp. 793-799) state that the read current for the described conventional SRAM two-dimensional memory cell array is 100 microamperes.
Vertically-stacked layers of memory cells have been described, as for example in U.S. Pat. No. 4,646,266 (“Ovshinsky”), U.S. Pat. No. 5,835,396 (“Zhang”), and U.S. Pat. No. 6,034,882 (“Johnson”), and PCT WO 99/14763 (“Gudesen”). Johnson and Zhang describe write-once memory arrays, while Ovshinsky and Gudesen describe re-writable memory arrays; however, none of these documents suggests the present invention as defined by the following claims.
BRIEF SUMMARY
Preferred embodiments described below include a memory array comprising a plurality of vertically-stacked layers of memory cells, each memory cell characterized by a read current that is less than 6.3 microamperes.
Because the read current is relatively small, small memory cells occupying a small chip area may be used. In this way manufacturing costs are minimized. The disclosed memory arrays are well-suited for use in applications that can tolerate longer-than-conventional read access times, and for which the dramatic cost reduction that is achieved is particularly attractive.
Other preferred embodiments described below include a three-dimensional memory array having multiple vertically stacked layers of memory cells, each memory cell having a respective antifuse layer. The memory cells are characterized by an average maximum read current of less than 500 microamperes when the respective antifuse layers are disrupted. The memory cells also include first and second diode components, each characterized by a dopant concentration greater than 10×10
19
/cm
3
. Boron dopant concentrations of 1×10
20
/cm
3
and 5×10
20
/cm
3
are disclosed. These high dopant levels provide the advantage of higher maximum read currents for a programmed memory cell.
This section has been provided by way of general introduction, and it is not intended to narrow the scope of the following claims.


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Edited by Cappelletti, Paulo et al., “Flash Memories”, Kluwer Academic Publishers, 1999.
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