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Multilevel memory devices with multi-bit data latches

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Multilevel non-volatile semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Multilevel register-file bit-read method and apparatus

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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Multilevel sense device for a flash memory

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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Multilevel sensing circuit and method thereof

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent

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Multilevel storage semiconductor memory read circuit

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Multimode data buffer and method for controlling propagation...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Multimode data buffer and method for controlling propagation...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Multiple access storage device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Multiple address outputs for programming the memory register...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Multiple bank memory with auto refresh to specified bank

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Multiple bit dynamic random-access memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Multiple bit line column redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Multiple bit line column redundancy with primary local and...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Multiple bit output dynamic random-access memory

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Multiple buffer memory interface

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Multiple bus charge sharing

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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Multiple discharge capable bit line

Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate

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Multiple dummy cell layout for MOS random access memory

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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Multiple equilibration circuits for a single bit line

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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