Multiple bank memory with auto refresh to specified bank

Details Multiple bank memory with auto refresh to specified bank Multiple bank memory with auto refresh to specified bank

1996-02-16

1997-05-06

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, 36523003, 365236, G11C 700

Patent

active

056277911

ABSTRACT:
A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an auto-refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.

REFERENCES:
patent: 5208779 (1993-05-01), Walther et al.
patent: 5291443 (1994-03-01), Lim
patent: 5335201 (1994-08-01), Walther et al.
patent: 5335202 (1994-08-01), Manning et al.
patent: 5446696 (1995-08-01), Ware et al.
patent: 5455801 (1995-10-01), Blodgett et al.
patent: 5511033 (1996-04-01), Jung

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