Multilevel memory devices with multi-bit data latches

Details Multilevel memory devices with multi-bit data latches Multilevel memory devices with multi-bit data latches

1998-12-18

2000-01-04

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365191, G11C 700

Patent

active

06011729&

ABSTRACT:
A multi-bit data latch includes a gated input buffer having a buffer input terminal, a buffer output terminal, and a buffer control terminal. The gated input buffer provides an output signal at the buffer output terminal responsive to an input signal applied to the buffer input terminal subject to a buffer control signal at the buffer control terminal. A first latch circuit has a first latch output terminal and a first latch input terminal, and a second latch circuit has a second latch output terminal and a second latch input terminal. A first switching circuit is operative to connect and disconnect the first latch input terminal to a reference voltage source responsive to an output signal at the buffer output terminal and to a first latch control signal. A second switching circuit is operative to connect and disconnect the second latch input terminal to the reference voltage source responsive to an output signal at the buffer output terminal and to a second latch control signal. A third switching circuit is operative to connect and disconnect the first latch output terminal to the reference voltage source responsive to an output signal at the buffer output terminal and to a third latch control signal. A reset circuit may be connected to the latch output terminals of the first and second latch circuits and operative to set the latch output terminals at a reference voltage source responsive to a reset signal.

REFERENCES:
patent: 5218569 (1993-06-01), Banks
patent: 5457650 (1995-10-01), Sugiura et al.
patent: 5761132 (1998-06-01), Kim
patent: 5768188 (1998-06-01), Park et al.
patent: 5784331 (1998-07-01), Lysinger

Affiliated with

Also associated with

Rating

Multilevel memory devices with multi-bit data latches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel memory devices with multi-bit data latches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel memory devices with multi-bit data latches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1077718