Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-12-22
2002-04-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S185030
Reexamination Certificate
active
06377497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory read circuit for changing the word voltage of a multilevel storage semiconductor memory by stages such as from second stage→first stage→third stage or from fourth stage→second stage→sixth stage→first stage→third stage→fifth stage→seventh stage. Particularly, the present invention relates to a multilevel storage semiconductor memory read circuit capable of reducing power consumption by shortening sense amplifier operation time.
2. Description of the Related Art
A conventional read method in a multilevel memory is to actuate a sense amplifier for each of the word voltages at respective stages and to obtain ON/OFF outputs according to the threshold voltage VT of a multilevel cell. Then, the output results of the word voltages at the respective stages are latched by latch circuits, the respective latched outputs are logically operated by an encoder and data is transmitted to an output circuit
FIG. 1
is a circuit diagram showing one example of the conventional read circuit.
FIG. 2
is a truth table of the circuit diagram.
FIG. 3
is a timing chart showing circuit operation. The output of a cell
712
of a read circuit
740
is inputted into a sense amplifier
713
and inputted from the sense amplifier
713
into a latch circuit group
711
. The latch circuit group
711
has latch circuits
742
,
741
and
743
for first to third stages, respectively. The outputs L
1
and L
3
of the first-stage latch circuit
742
and the third-stage latch circuit
743
, respectively, are inputted into an EOR logic gate
715
of an encoder circuit
717
. The output of the EOR logic gate
715
and the output L
2
of the second-stage latch circuit
741
are inputted, as superordinate data B
1
and subordinate data B
0
, into an output circuit
718
, respectively.
Next, the operation of the conventional read circuit will be described. First, at an interval T
1
, the level of a signal ø
2
for setting a word voltage at the second stage is “H” and the sense amplifier
713
, therefore, reads a cell when the word level is at the second stage. As shown in the truth table of
FIG. 2
, since a VT1 cell is turned on at the second-stage word level, a “L” data indicating that the read cell is turned “ON” is outputted from the sense amplifier.
Next, when the interval moves from T
1
to T
2
, the level of the signal ø
2
inputted into the latch circuit
741
changes from “H” to “L”. Due to this, the output data of the sense amplifier
713
is latched by the second-stage latch circuit
741
and transmitted, through the encoder circuit
717
, to the output circuit
718
as the subordinate data B
0
. Namely, at this point, the subordinate data B
0
on the truth table shown in
FIG. 2
is determined. Also, since the level of the latch signal ø
2
is “L” during the intervals T
2
and T
3
, the level of the latch data L
2
remains “L” until an interval T
4
.
Further, at the interval T
2
, the level of a signal ø
1
for setting a word voltage at the first-stage voltage is “H” and the sense amplifier
713
, therefore, outputs data when the word level is at the first stage.
Next, when the interval moves from T
2
to T
3
, the level of the signal ø
1
inputted into the latch circuit
742
changes from “H” to “L” and the output data of the sense amplifier
713
is, therefore, latched by the first-stage latch circuit
742
, As in the case of the above, since the level of the latch signal ø
1
is “L” during the intervals T
3
and T
4
, the latch data L
1
is maintained until the next interval T
5
.
At the interval T
3
, the level of a signal ø
3
for setting a word voltage at the third-stage voltage is “H” and the sense amplifier
713
, therefore, outputs data when the word level is at the third stage.
Next, when the interval moves from T
3
to T
4
, the level of the signal ø
3
inputted into the latch circuit
743
changes from “H” to “L”. Due to this, the output data of the sense amplifier
713
is latched by the third-stage latch circuit
743
. As in the case of the above, since the level of the latch signal ø
3
is “L” during the intervals T
4
and T
5
, the latch data L
3
is maintained until the next interval T
6
. The latch data is then transmitted, through the third-stage latch circuit
743
, to the encoder circuit
717
, operated with the first-stage latch output L
1
by the EOR logic gate
715
and the superordinate data B
1
is thereby determined and transmitted to the output circuit
718
. Namely, at this point, the superordinate data B
1
on the truth table shown in
FIG. 2
is determined. Through the above-stated circuit operation, the sense amplifier
713
in this example constantly operate with word voltages at the respective stages when reading one cell
712
.
The conventional circuit, however, has the following disadvantages. It is obvious that a cell turned on as a result of reading the second-stage cell is also turned on at the third-stage word voltage. In addition, it is obvious that a cell turned off as a result of reading the second-stage cell is also turned off at the first-stage word voltage. However, since the sense amplifier constantly operates to latch sense amplifier outputs at the respective word voltages, excessive power is consumed.
The basic constitution of a multilevel storage semiconductor memory is described in Japanese Patent Application Laid-Open No. 1-196791. A multilevel memory capable of reducing the number of sense amplifiers to allow reducing chip area is described in Japanese Patent Application Laid-Open No. 7-37393. A multilevel memory intended to accelerate data reading speed is described in Japanese Patent Application Laid-Open No. 10-11982. A semiconductor memory capable of reading minute multilevel data is described in Japanese Patent Application Laid-Open No. 11-110974. None of these prior arts described in the publications are, however, intended to reduce power consumption based on sense amplifier operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multilevel storage semiconductor memory capable of removing excessive sense amplifier operation and reducing sense amplifier power consumption by using sense amplifier operation stop circuit and latch input correction circuit.
A multilevel storage semiconductor memory read circuit according to the present invention is for applying a plurality of stages of word voltages to one cell and latching data according to respective word voltage levels, and comprises a sense amplifier reading the cell; a latch circuit group consisting of a plurality of latch circuits and latching the data according to the respective word voltage levels; an encoder circuit converting outputs of the latch circuits into binary data; a stop and correction circuit stopping a circuit operation of the sense amplifier when a different-stage latch circuit performs a read operation based on an output result of a specified-stage latch circuit, and applying a signal expected to be outputted from the sense amplifier, which is being stopped, as an input signal L
0
of the latch circuit group.
In case of, for example, a four-level cell with three latch circuits of the first-stage latch circuit, the second-stage latch circuit and the third-stage latch circuit, the cell turned on as a result of reading the cell at the second stage has a lower cell threshold value than a second-stage word voltage and the cell is obviously turned on when read at a third-stage word voltage higher than the second-stage word voltage. The cell turned on as a result of reading the cell at the second stage has a higher cell threshold value than the second-stage word voltage and the cell is obviously turned off when read at the first-stage word voltage lower than the second-word voltage. According to the present invention, the operation of the sense amplifier is stopped only in such a case of reading the cell as to satisfy these two conditions. In addition, by supplying data expected to be outputted from the sen
Hayes & Soloway P.C.
Le Vu A.
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