Multiple equilibration circuits for a single bit line

Details Multiple equilibration circuits for a single bit line Multiple equilibration circuits for a single bit line

1999-10-15

2000-12-26

Phan, Trong

Static information storage and retrieval

Read/write circuit

Precharge

G11C 700

Patent

active

061669768

ABSTRACT:
According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

REFERENCES:
patent: 5291433 (1994-03-01), Itoh
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5691933 (1997-11-01), Takenaka
patent: 5701268 (1997-12-01), Lee et al.
patent: 5740113 (1998-04-01), Kaneko
patent: 5768199 (1998-06-01), Inoue
patent: 6034884 (2000-03-01), Jung

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