Multiple bus charge sharing

Details Multiple bus charge sharing Multiple bus charge sharing

2007-06-15

2009-08-25

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S063000, C365S149000, C365S210120

Reexamination Certificate

active

07580304

ABSTRACT:
A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.

REFERENCES:
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patent: 7295456 (2007-11-01), Ogiwara et al.
patent: 2008/0285327 (2008-11-01), Ogiwara et al.
Yamauchi, Hiroyuki, Akamatsu, Hironori, Fujita, Tsutomu, An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's, IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 423-431.
Rajapandian, Saravanan, Shepard, Kenneth L., Hazucha, Peter, Karnik, Tanay, High-Voltage Power Delivery Through Charge Recycling, IEEE Journal of Solid-State Circuits, vol. 41, No. 6, Jun. 2006, pp. 1400-1410.

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