Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-01-26
2003-04-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189120
Reexamination Certificate
active
06542413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multiple access storage devices, and more specifically to a parallel memory device that can be used to replace a plurality of large shift registers.
2. Description of Related Art
A serial-type architecture is typically used to make computation devices for numbers encoded with a large number of bits. The main advantage of serial-type architectures is that they considerably reduce the number of computation elements (e.g., adder, subtracter, multiplier, and the like). However, some elements used in serial architectures have a size that is slightly greater than in parallel architectures. These are the storage elements, and namely shift registers.
This drawback can be identified more clearly in an exemplary modular arithmetic coprocessor with a series architecture, such as those disclosed in EP-A-0 601 907, EP-A-0 712 070, EP-A-0 712 071, EP-A-0 712 072, EP-A-0 778 518, EP-A-0 784 262, EP-A-0 785 502, EP-A-0 785 503, EP-A-0 793 165, EP-A-0 853 275, WO/97 25668, and European Patent Application No. 98-470020.3 (filed Aug. 26, 1998). As shown in these references, three or four large registers (depending on the application) having a size of 256, 512, 1024, or more bits are used. Furthermore, the large registers may be arranged differently in order to give a variable size that provides flexibility, and to reduce the consumption of the registers.
FIG. 1
, which corresponds to
FIG. 1
of European Patent Application No. 98-470020.3, shows a modular arithmetic coprocessor. The coprocessor
1
includes four m×Bt bit shift registers
2
to
5
, where m and Bt are conventionally equal to a power of two (for example, 8 or 16 for m and 32 or 64 for Bt); four multiplexers
6
to
9
that are associated with each of the four registers
2
to
5
, respectively; computation circuitry
10
,
11
,
19
,
20
,
26
,
29
, and
35
of the series adder, series subtracter, and series multiplier type; storage
17
,
18
,
22
,
23
, and
25
of the series/parallel register type and transparent latch circuit type for storing Bt bit words; delays
28
,
32
and
33
for introducing delays of Bt clock cycles; and multiplexers
12
to
16
,
21
,
24
,
27
,
30
,
31
,
34
,
37
, and
38
for transmitting data between the other elements of the coprocessor
1
. The coprocessor
1
can perform different modular and non-modular operations by shifting the data in one or more of the four registers
2
to
5
. Further information on the operation of the coprocessor
1
is available in the references mentioned above, which are herein incorporated by reference.
A coprocessor
1
of this kind can be used in a chip card along with a memory and a standard microprocessor, which controls the coprocessor. The coprocessor
1
is typically used to perform computations for encryption. Because the size of the keys used in encryption is constantly increasingly, these keys require the use of increasingly bigger (at present 512-bit or 1024-bit) registers
2
to
5
. The size of these registers amounts to about 40% of the surface area of the coprocessor
1
. Furthermore, the use of shift registers requires serial loading of the data. This is particularly detrimental to the performance of the circuit during data exchanges between the memory and the coprocessor
1
. Additionally, the use of the registers leads to a loss of time when exchanging the contents of two registers.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a smaller storage device having greater flexibility for data transfers. The present invention is not restricted to use with a modular arithmetic coprocessor, but can be applied to any computation device that uses serial type data routing and at least one relatively large register.
One embodiment of the present invention provides a storage device that includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers.
Another embodiment of the present invention provides a coprocessor of the type that includes a series input terminal, a series output terminal, and computation elements located on at least one data path between the series input terminal and the series output terminal. The coprocessor includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. The series input terminal is coupled to the output of the first shift register, and the output terminal is coupled to the input of the second shift register. In one preferred embodiment, the memory consists of two independent memories that each have k′-bit data access (where k=2×k′), and one of the independent memories is coupled to the least significant lines of the data bus and the other independent memory is coupled to the most significant lines of the data bus.
Yet another object of the present invention provides an IC chip card that includes a microprocessor, storage, and a coprocessor. The coprocessor includes a series input terminal; a series output terminal; computation elements located on at least one data path between the series input terminal and the series output terminal; at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. The series input terminal is coupled to the output of the first shift register, and the output terminal is coupled to the input of the second shift register. In a preferred embodiment, the coprocessor also includes a third k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a third k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the third latch circuit; a fourth k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; and a fourth k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the fourth latch circuit.
Other objects, features, and advantages of the
Plessier Bernard
Pomet Alain
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Hoang Huan
STMicroelectronics S.A.
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