Multiple dummy cell layout for MOS random access memory

Details Multiple dummy cell layout for MOS random access memory Multiple dummy cell layout for MOS random access memory

1978-06-15

1980-04-15

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365205, G11C 700

Patent

active

041986970

ABSTRACT:
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A plurality of dummy cells are connected to each column line half instead of a single dummy cell, and one of the dummy cells is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by spacing the dummy cells along each column line half, and addressing a dummy cell which is spaced about the same distance from the sense amplifier as the selected memory cell on the other side.

REFERENCES:
patent: 4038646 (1977-07-01), Mehta et al.
patent: 4050061 (1977-09-01), Kitagawa
patent: 4117545 (1978-09-01), Inadachi
patent: 4118794 (1978-10-01), Mizuno et al.

Affiliated with

Also associated with

Rating

Multiple dummy cell layout for MOS random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple dummy cell layout for MOS random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple dummy cell layout for MOS random access memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-478656