Flexible memory architectures for programmable logic devices

Flexible memory architectures for programmable logic devices

Flexible redundancy architecture and fuse download scheme

Flexible redundancy for memories

Flexible word line boosting across VCC supply

Flip-flop with additional state storage in the event of...

Floating bitline test mode with digitally controllable bitline e

Floating bitline timer allowing a shared equalizer DRAM...

Floating body control in SOI DRAM

Floating gate nonvolatile memory with reading while writing capa

Floating gate nonvolatile memory with uniformly erased threshold

Floating gate nonvolatile memory with uniformly erased threshold

Floating isolation gate for DRAM sensing

Floating isolation gate from DRAM sensing

Floating-body DRAM using write word line for increased...

Floating-body DRAM using write word line for increased...

Flood mode implementation for continuous bitline local...

Flood mode implementation for continuous bitline local...

Folded bit line memory with one decoder per pair of spare rows

Folded bit line memory with one decoder per pair of spare rows