Floating bitline timer allowing a shared equalizer DRAM...

Details Floating bitline timer allowing a shared equalizer DRAM... Floating bitline timer allowing a shared equalizer DRAM...

1999-07-22

2001-02-20

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S233100, C365S202000, C365S196000

Reexamination Certificate

active

06191988

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to sense amplifiers and more particularly to a new sense amplifier having a shared equalizer circuit and a timer circuit to prevent the inactive bitlines from floating for long time periods.
2. Description of the Related Art
Integrated circuit memory devices are commonly divided into arrays of memory cells. Usually only one of the arrays is activated during a given access cycle to reduce power consumption and increase the efficiency of the integrated circuit. Because of this operation, a sense amplifier or an array of sense amplifiers are positioned between the memory cell arrays. This allows the sense amplifier to be shared by adjacent arrays, thereby decreasing chip area consumed by the memory device, decrease the production costs and increasing processing speed.
A conventional shared dynamic random access memory (DRAM) sense amplifier (SA) is shown in FIG.
1
. The sense amplifier includes equalizer circuits
103
,
109
which are supplied with bitline equalization voltages
102
,
111
. The equalizer circuits
103
,
109
are outside the multiplexors
104
,
108
. Additionally data lines
107
are selected by a column select signal
110
. A cross-coupled pair of NFETs
105
and a cross-coupled pair of PFETs
106
are also part of the same sense amplifier and perform the signal sensing and data latching functions of the sense amplifier. The bitlines
100
,
101
which are connected to the adjacent arrays are also illustrated. Having two multiplexor (MUX) devices
104
,
108
allows the sense amplifier to service two arrays, thus increasing layout efficiency.
During a precharging operation, the sets of bitlines
100
,
101
are adjusted to an equalizing potential which is generally midway between the active bitline high potential and the active bitline low potential. During the active phase of the row cycle, one each pair of active bitlines is raised to the active bitline high level and the other is lowered to the active bitline low level. During the precharge phase of the row cycle, these bitlines are connected together and equalized to a voltage midway between the active bitline high and low levels.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for a dynamic random access memory chip including memory element arrays having bitlines, a sense amplifier shared by the arrays (the sense amplifier includes multiplexors connected to the bitlines and an equalizer circuit) and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.
The second bitlines are connected to active arrays. The time period is approximately 1 &mgr;s. The timer circuit can include a plurality of timer circuits, where one of the timer circuits is connected to each of the arrays, is connected to each bank of the arrays, or is connected to each of the sense amplifiers. The sense amplifier includes only one equalizer circuit which equalizes both the first bitlines and the second bitlines.
The invention also comprises a method of equalizing bitlines in memory element arrays having a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, and an equalizer circuit connected to the multiplexors. The method includes beginning a sensing of first bitlines, allowing a time period to elapse and connecting second bitlines to the sense amplifier. The time period is less than the active phase of the row cycle. The first bitlines are connected to an active array. The time period is approximately 1 &mgr;s. The sense amplifier includes only one equalizer circuit. The timer circuit allows the elapsing of the time period.
The invention allows the use of a sense amplifier serving multiple arrays that can properly operate with a single equalizer circuit without causing an excessive current demand on the bitline equalization voltage source. Thus, the invention reduces the cost, complexity and the space required for a sense amplifier.


REFERENCES:
patent: 4941128 (1990-07-01), Wada et al.
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5521869 (1996-05-01), Ishimura et al.
patent: 5684736 (1997-11-01), Chan
patent: 5715189 (1998-02-01), Asakura
patent: 5973991 (1999-10-01), Tsuchida et al.

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