Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1982-11-24
1985-01-15
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365189, 365210, G11C 1140
Patent
active
044942206
ABSTRACT:
A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.
REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4274013 (1981-06-01), Clemons et al.
patent: 4351034 (1982-09-01), Eaton et al.
Dumbri Austin C.
Procyk Frank J.
AT&T Bell Laboratories
Fears Terrell W.
Ostroff Irwin
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