Flexible memory architectures for programmable logic devices

Details Flexible memory architectures for programmable logic devices Flexible memory architectures for programmable logic devices

2011-06-07

2011-06-07

Sofocleous, Alexander (Department: 2824)

Static information storage and retrieval

Read/write circuit

Using different memory types

C326S039000, C365S189080, C365S230050

Reexamination Certificate

active

07957208

ABSTRACT:
In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

REFERENCES:
patent: 5548228 (1996-08-01), Madurawe
patent: 5640107 (1997-06-01), Kruse
patent: 5689516 (1997-11-01), Mack et al.
patent: 5696455 (1997-12-01), Madurawe
patent: 5794033 (1998-08-01), Aldebert et al.
patent: 6038185 (2000-03-01), Ng et al.
patent: 6044025 (2000-03-01), Lawman
patent: 6049222 (2000-04-01), Lawman
patent: 6150837 (2000-11-01), Beal et al.
patent: 6304099 (2001-10-01), Tang et al.
patent: 6356107 (2002-03-01), Tang et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6507214 (2003-01-01), Snyder
patent: 6538468 (2003-03-01), Moore
patent: 6564285 (2003-05-01), Mills et al.
patent: 6704850 (2004-03-01), Reynolds
patent: 6714041 (2004-03-01), Darling et al.
patent: 6721840 (2004-04-01), Allegrucci
patent: 6732263 (2004-05-01), May et al.
patent: 6772230 (2004-08-01), Chen et al.
patent: 6774668 (2004-08-01), Wirtz, II
patent: 6785165 (2004-08-01), Kawahara et al.
patent: 6828823 (2004-12-01), Tsui et al.
patent: 6851047 (2005-02-01), Fox et al.
patent: 6873177 (2005-03-01), Wennekamp et al.
patent: 6903574 (2005-06-01), Chen et al.
patent: 7088132 (2006-08-01), Tang et al.
patent: 7095247 (2006-08-01), Tang et al.
patent: 7099189 (2006-08-01), Plants
patent: 7190190 (2007-03-01), Camarota et al.
patent: 7196963 (2007-03-01), Fenstermaker et al.
patent: 7227380 (2007-06-01), Elftmann et al.
patent: 7242218 (2007-07-01), Camarota et al.
patent: 7375549 (2008-05-01), Tang et al.
patent: 7378873 (2008-05-01), Tang et al.
patent: 7459931 (2008-12-01), Tang et al.
patent: 7538574 (2009-05-01), Tang et al.
patent: 7554357 (2009-06-01), Chen et al.
patent: 7554358 (2009-06-01), Fontana et al.
patent: 2004/0061147 (2004-04-01), Fujita et al.
patent: 2004/0064622 (2004-04-01), Smith
patent: 2005/0189962 (2005-09-01), Agrawal et al.
ATMEL Corporation, AT17LV(A) Series FPGA Configuration Memory, Ref. 0437K-CNFG, May 2003, pp. 1-18.
ATMEL Corporation, FPGA Configuration EEPROM Memory, 2322F-CNFG, Jun. 2006, pp. 1-18.
ATMEL Corporation, FPGA Configuration EEPROM Memory, 2321 E-CNFG, Jun. 2003, pp. 1-18.
Lattice Semiconductor Corporation, MachXO Family Data Sheet, Version 02.1, May 2006, pp. 1-93.
Altera, Section III User Flash Memory, Max II Device Handbook, vol. 1, 2005, 80 pages.
Actel, ProASIC 3 Flash Family FPGAs with Optional Soft ARM Support, Advanced v0.6, Apr. 2006, 208 pages.
Altera Corporation, Cyclone Device Handbook, vol. 1, 13. Configuring Cyclone FPGAs, Aug. 2005, 50 pages.
Lattice Semiconductor Corporation, Low-Cost FPGA Configuration Via Industry-Standard SPI Serial Flash, A Lattice Semiconductor White Paper, Jun. 2004, 13 pages.
Xilinx, Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories, Arthur Khu, Jan. 3, 2006, 16 pages.
ST Microelectronics, M25P80, 8 Mbit Low Voltage Serial Flash Memory with 40 MHz SPI Bus Interface, Aug. 2004, 41 pages.
Lattice Semiconductor Corporation, ispXP Configuration Usage Guidelines, Technical Notes TN1026, Aug. 2002, pp. 1-18.
Lattice Semiconductor Corporation, ispXPGA Family, Data Sheet, Jul. 2005, 115 pages.
Lattice Semiconductor Corporation, ispXPGA Family, Preliminary Data Sheet, Dec. 2002, pp. 1-90.
Lattice Semiconductor Corporation, LatticeXP Family Data Sheet, Version 01.0, Feb. 2005, 77 pages.
Altera, Max II Device Handbook, http://www.altera.com, M115V-1.7, Jun. 2005, 330 pages.
Xilinx, on the Fly Reconfiguration with CoolRunner-II CPLDs, Application Note: CoolRunner-II CPLDs, May 2003, pp. 1-10.
Actel, ProASIC Plus Flash Family FPGAs, v.5.3, May 2006, 173 pages.
Actel, ProASIC 3 Flash Family FPGAs, ARM7 Soft IP Support in ProASIC3E ARM7-Ready Devices, Oct. 2005, 166 pages.
Lattice Semiconductor Corporation, Lattice XP Family Data Sheet, v.04.6, Jun. 2006 and earlier, 36 pages.
Lattice Semiconductor Corporation, MachXO Family Data Sheet, v.02.1, May 2006 and earlier, 30 pages.

Affiliated with

Also associated with

Rating

Flexible memory architectures for programmable logic devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flexible memory architectures for programmable logic devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flexible memory architectures for programmable logic devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2725647