Floating body control in SOI DRAM

Details Floating body control in SOI DRAM Floating body control in SOI DRAM

2006-09-21

2008-10-21

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S210130, C365S233100

Reexamination Certificate

active

07440353

ABSTRACT:
A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line (or bit line bar circuit). The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.

REFERENCES:
patent: 4370737 (1983-01-01), Chan
patent: 5392240 (1995-02-01), Muraoka
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 5877978 (1999-03-01), Morishita et al.
Tomishima, S.; Morishita, F.; Tsukude, M.; Yamagata, T.; Arimoto, K.; A Long Data Retention SOI-DRAM With the Body Refresh Function; VLSI Circuits, 1996 Digest of Technical Papersl, 1996 Symposium on Jun. 13-15, 1996 pp. 198-199.

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