Circuit for locking a delay locked loop (DLL) and method...

Circuit for setting one of a plurality of organization forms...

Circuit for transmitting and receiving data and control...

Circuit using a shared delay locked loop (DLL) and method...

Circuitry for reducing parasitic coupling in core memory

Clock control circuit

Clock control circuit

Clock control circuit

Clock control circuit

Clock driver device and semiconductor memory apparatus...

Clock driver in semiconductor memory device

Clock generating circuit having additional delay line...

Clock generating circuit with multiple modes of operation

Clock generation circuit for analog value memory circuit

Clock signal generating circuit and data output apparatus...

Clock synchronous memory

Clock synchronous semiconductor memory device having a...

Clock synchronous semiconductor memory device having a...

Clock synchronous type semiconductor memory device

Clocked memory with delay establisher by drive transistor design