Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-06-30
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
06292412
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-187052, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to the clock synchronous circuit which is used in semiconductor devices, such as double data rate synchronous DRAM, especially to the clock synchronous circuit suitable for such devices as those which perform synchronous control by using a high-speed clock.
In recent years, clock synchronous type memories, such as synchronous DRAM, are used in computer systems, reflecting demands for high-speed processing. Such a clock synchronous type memory utilizes the clock, which synchronizes with the clock supplied from the outside of the memory (to be referred to as the external clock hereinafter) to control internal operation, by generating it inside the memory.
In case a synchronous lag takes place between the clock used inside the memory (to be referred to as the internal clock hereinafter) and the external clock, it will be liable to cause mis-operation in the internal circuit of the memory especially in high-speed processing even if the lag is very small. Furthermore, the use of the internal clock, which has a synchronous lag arising between it and the external clock, hinders high-speed operation on the side of the controller using data read from the memory.
Thus recent memories are beginning to be mounted with clock synchronous circuits which are designed to synchronize the internal clock to the external clock with high precision.
However, while memories mounted with clock synchronous circuits are capable of performing stable high-speed operation, their power consumption become larger correspondingly, compared with the memories which are not mounted with clock synchronous circuits.
In order to reduce such a disadvantage, it is desired to reduce power consumption by halting the operation of the clock synchronous circuit as far as possible when the internal circuit of the memory does not require the internal clock outputted from the clock synchronous circuit.
However, conventional clock synchronous circuits are not capable of reducing power consumption in actual practice even by halting the operation because they have no established methods for halting and controlling the operation nor established halt control circuits.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the objects of the present invention are to reduce power consumption by halting the generating operation of the internal clock when it is not needed, as well as to provide the clock synchronous circuit which is capable of resuming the generation of the stable clock output when the operation is needed.
According to the first aspect of the present invention, a clock synchronous circuit is provided, comprising a clock receiver for receiving an external clock signal; a delay monitor for receiving and delaying an output of the clock receiver; a first delay circuit for receiving and delaying an output of the delay monitor; a second delay circuit for receiving an output of the clock receiver in a cycle next to the signal delayed by the first delay circuit, and for delaying the output by a delay time substantially equal to a delay time of the first delay circuit; a driver for receiving an output of the second delay circuit and outputting an internal clock signal; a first gate circuit provided between the clock receiver and the delay monitor, for controlling supplying of the output of the clock receiver to the delay monitor, in accordance with a first control signal; and a second gate circuit provided between the delay monitor and the first delay circuit, for controlling supplying of the output of the delay monitor to the first delay circuit, in accordance with a second control signal.
According to the second aspect of the present invention, a clock synchronous circuit is provided, comprising a clock receiver for receiving an external clock signal; a first gate circuit for receiving at least an output of the clock receiver and a first control signal and controlling supplying of the output of the clock receiver in accordance with the first control signal; a delay monitor for receiving and delaying an output of the first gate circuit; a second gate circuit for receiving an output of the delay monitor and a second control signal and controlling supplying of the output of the delay monitor in accordance with a second control signal; a forward pulse delay circuit including a plurality of first delay units connected in cascade, designed to receive the output of the second gate circuit, each of the first delay units delay the output by a specific time, respectively, and supply the output as a forward pulse to the following first delay unit; a backward pulse delay circuit including a plurality of second delay units connected in cascade, designed to receive the output of the clock receiver, each of the second delay units delay the pulse for a specific time, respectively, and supply the output as a backward pulse to the following second delay unit; a driver for receiving the backward pulse supplied from the backward pulse delay circuit and generating an internal clock signal from the backward pulse; a state-holding section including a plurality of state-holding circuits associated with the first delay units and second delay units, the state-holding section being one designed to control the second delay units such that each state-holding circuit comes to hold a set state when the associated first delay unit receives a forward pulse and a reset state when the associated second delay unit receives a backward pulse and that the output of the clock receiver is input as a backward pulse to any second delay unit that is associated with a state-holding circuit which comes to hold a reset state after the output of the delay monitor is input to the forward pulse delay circuit and. before the backward pulse is propagated through the back pulse delay circuit; a third gate circuit for receiving the output of the clock receiver, the first control signal and a third control signal and controlling the output of the clock receiver in accordance with the first control signal and the third control signal; a control pulse generating circuit for receiving the output of the clock receiver and the second control signal, controlling the output of the third gate circuit in accordance with the second control signal, and generating a first control pulse for resetting the first delay units; a state-holding circuit for receiving the first control pulse and generating the second control pulse for resetting some of the state-holding circuits provided in the state-holding section, in accordance with the first control pulse; and a control signal generating circuit for generating the first, second and third control signals.
According to the third aspect of the present invention, a clock synchronous circuit is provided, comprising a first clock receiver for receiving a first external clock signal; a first delay monitor for receiving and delaying an output of the first clock receiver; a first delay circuit for receiving and delaying an output of the first delay monitor; a second delay circuit for receiving the output of the first clock receiver in a cycle next to the signal delayed by the first delay circuit, and for delaying the output by a delay time substantially equal to a delay time of the first delay circuit; a first driver for receiving an output of the second delay circuit and generating a first internal clock signal; a first gate circuit provided between the first clock receiver and the first delay monitor, for controlling supplying of the output of the first clock receiver to the first delay monitor in accordance with a first control signal; a second gate circuit provided between the first delay monitor and the first delay circuit, for controlling supplying of the output of the first display monitor to the first delay circuit in accordance with a second control s
Kamoshida Masahiro
Kato Koji
Ohshima Shigeo
Ohtake Hiroyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nelms David
Tran M.
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