Clock signal generating circuit and data output apparatus...

Details Clock signal generating circuit and data output apparatus... Clock signal generating circuit and data output apparatus...

2011-08-02

2011-08-02

Le, Vu A (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

07990784

ABSTRACT:
A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

REFERENCES:
patent: 2002/0105838 (2002-08-01), Maruyama et al.
patent: 2002/0144170 (2002-10-01), Mullarkey
patent: 2002/0176292 (2002-11-01), Akasaki et al.
patent: 2002/0178322 (2002-11-01), Gans et al.
patent: 2007/0146039 (2007-06-01), Koo
patent: 2008/0001638 (2008-01-01), Choi
patent: 10-0638747 (2006-07-01), None
patent: 10-0753036 (2007-04-01), None

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