Circuit for locking a delay locked loop (DLL) and method...

Details Circuit for locking a delay locked loop (DLL) and method... Circuit for locking a delay locked loop (DLL) and method...

2011-01-11

2011-01-11

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S233100, C365S233190

Reexamination Certificate

active

07869287

ABSTRACT:
A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.

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