Circuit for transmitting and receiving data and control...

Details Circuit for transmitting and receiving data and control... Circuit for transmitting and receiving data and control...

2008-12-17

2011-10-11

Le, Vu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000

Reexamination Certificate

active

08036050

ABSTRACT:
A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.

REFERENCES:
patent: 6317377 (2001-11-01), Kobayashi
patent: 7319730 (2008-01-01), Okuda et al.
patent: 2006/0233031 (2006-10-01), Jakobs
patent: 2000-048567 (2000-02-01), None
patent: 1020060062426 (2006-06-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Mar. 30, 2010.

Affiliated with

Also associated with

Rating

Circuit for transmitting and receiving data and control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for transmitting and receiving data and control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for transmitting and receiving data and control... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4283687