Clock control circuit

Details Clock control circuit Clock control circuit

1998-10-29

1999-11-16

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

327269, 327276, G11C 700

Patent

active

059869496

ABSTRACT:
An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

REFERENCES:
patent: 5361277 (1994-11-01), Grover
patent: 5367490 (1994-11-01), Akimoto et al.
patent: 5376849 (1994-12-01), Dickol et al.
patent: 5390224 (1995-02-01), Komatsuda
patent: 5469110 (1995-11-01), Liao
patent: 5566129 (1996-10-01), Nakashima et al.
patent: 5602798 (1997-02-01), Sati et al.
patent: 5684424 (1997-11-01), Felix et al.
patent: 5783959 (1998-07-01), Yokoyama
patent: 5864564 (1999-01-01), Levitt et al.

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