Clock generating circuit having additional delay line...

Details Clock generating circuit having additional delay line... Clock generating circuit having additional delay line...

2000-09-06

2002-01-15

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C327S291000, C327S298000

Reexamination Certificate

active

06339553

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit used for a semiconductor memory device. More specifically, the present invention relates to a clock generating circuit generating, by a digital DLL (Delay Locked Loop), an internal clock synchronous with an externally applied reference clock, and to a semiconductor memory device provided with the clock generating circuit.
2. Description of the Background Art
For generating a clock signal in a semiconductor memory device, a technique has been known in which a clock generating circuit employing a digital DLL (Delay Lock Looped) (hereinafter also simply referred to as a DLL circuit) is used to delay phase of an externally applied reference clock signal to generate an internal clock signal synchronized with the external clock. This technique is of particular importance in a synchronous semiconductor memory device (SDRAM: Synchronous Dynamic Random Access Memory). Recently, a DDR-SDRAM (Double Data Rate SDRAM) capable of outputting data at the timings of both rising and falling edges of the external clock signal to attain higher speed of operation has been developed.
FIG. 31
is a timing chart representing operation timings of the DDR-SDRAM.
Referring to
FIG. 31
, reference character ext.CLK represents an external reference clock signal which repeatedly rises and falls at the period of Tc. In the DDR-SDRAM, data DQ is output both at the rising edge and the falling edge of ext.CLK. In order to output data at timings synchronized with ext.CLK, it is necessary to generate in the semiconductor memory device an internal clock pulse int.CLKP as a trigger, at a timing earlier by a data output delay time To consumed by a data output buffer than the timing of rising and falling edges of ext.CLK.
Further, in the DDR-SDRAM, generally, “SSTL2” is used as an interface standard for the clock input signal generally.
FIG. 32
is a timing chart representing SSTL2 standard.
In STTL2, external clock signal ext.CLK and an inverted signal /ext.CLK thereof as complementary signals are used to define a rising edge of the clock at a timing when signal levels satisfy the condition of ext.CLK>/ext.CLK and conversely, the falling edge at the timing when /ext.CLK>ext.CLK.
As the data DQ is output in response to the rising and falling edges, the two output periods of data output corresponding to one period of the external clock signal are represented as a period tCH from a rising edge to the falling edge of the clock and a time period tCL from the falling edge to the rising edge. In the DDR-SDRAM, the ratio between tCH and tCL should desirably be 50:50, and SSTL2 standard requires that the ratio is within the range of 55:45 to 45:55.
FIG. 33
is a block diagram representing a configuration of a conventional DDL circuit
1000
used in a synchronous semiconductor memory device.
Referring to
FIG. 33
, DLL circuit
1000
includes: a clock input buffer
1010
receiving external clock signal ext.CLK and reference voltage Vref and outputting a clock signal BufCLK; a delay circuit
120
receiving clock signal BufCLK, adding a delay time in accordance with a count data ADR<
0
:M−1> and outputting the result; a level shifter
130
for changing voltage level of an output signal from delay circuit
120
; a delay replica circuit
140
adding a prescribed delay time to the output of level shifter
130
and outputting a feedback clock signal FBCLK; and a phase difference control circuit
150
controlling phase difference between feedback clock signal FBCLK and clock signal BufCLK.
FIG. 34
is a circuit diagram representing a configuration of a clock input buffer
1010
.
Referring to
FIG. 34
, clock input buffer
1010
has P type MOS transistors QPa and QPb as well as N type MOS transistors QNa and QNb constituting a current mirror amplifier comparing input voltage levels at input nodes Ni
1
and Ni
2
, amplifying difference between the voltage levels and outputting the difference to node Nb, and an inverter IVa outputting a signal in accordance with the voltage level at node Nb to node No. The clock signal BufCLK is output to node No.
Again referring to
FIG. 33
, phase difference control circuit
150
includes: a phase comparing circuit
152
comparing phases of clock signal BufCLK and feedback clock signal FBCLK and outputting count designating signals DWN, UP and LCK and a count clock signal cntclk in accordance with the result of comparison; and an up/down count circuit
154
setting the delay control amount count data ADR<
0
:M−1> in accordance with the count designating signals.
Up/down count circuit
154
updates count data ADR<
0
:M−1> in order to increase/decrease the delay control amount so that clock signals ext.CLK and FBCLK are synchronized, in accordance with the signal levels of count designating signals DWN, UP and LCK. Count data ADR<
0
:M−1> is a signal of M (M: natural number) bits representing the counted delay control amount.
In a locked state, feedback clock signal FBCLK is delayed by exactly one period (Tc) from clock signal BufCLK. At this time, feedback clock signal FBCLK has its phase delayed by Tc+Ti (Ti: delay time generated in clock input buffer) from the external clock signal ext.CLK. Similarly, clock signal int.CLKD has its phase delayed by Tc−To (To: delay time generated in output buffer) from the external clock signal.
The clock int.CLKD output from level shifter
130
is transmitted to pulse generating circuit
1060
. Pulse generating circuit
1060
outputs internal clock pulse int.CLKP in response to the rising and falling edges of clock signal ext.CLKD.
FIG. 35
is a circuit diagram representing configuration of pulse generating circuit
1060
.
Referring to
FIG. 35
, pulse generating circuit
1060
includes: a one shot pulse generating circuit
1062
generating a one shot pulse in response to a rising edge of clock signal int.CLKD; and a one shot pulse generating circuit
1064
generating a one shot pulse in response to a falling edge of clock
Referring to
FIG. 37
, delay unit
200
-m has clocked inverters CIVa and CIVb operating in response to a control signal R<m> from decode circuit
210
-m. Clocked inverter CIVa operates when the control signal R<m> is activated (H level), inverts the clock signal BufCLK and outputs the result. Clocked inverter CIVb operates when control signal R<m> is inactive (L level), inverts an output of the delay unit of the preceding stage and outputs the result.
Delay unit
200
-m further includes an inverter IVc. Inverter IVc has an input node connected to output nodes of clocked inverters CIVa and CIVb. An output of inverter IVc is applied to an input node of clocked inverter CIVb in the delay unit
200
-(m+1) of the succeeding stage.
Because of this configuration, when the corresponding control signal R<m> is active, delay unit
200
-m delays clock signal BufCLK and transmits it to the delay unit of the succeeding unit, and when the control signal R<m> is inactive, the delay unit further delays the delay unit input/output signal of the preceding stage and transmits the result to the delay unit of the succeeding stage. The signal output from IVc of delay unit
200
-
0
is transmitted to a level shifter
130
. An input node of CIVb of delay unit
200
-n is coupled to the ground voltage.
In the conventional DLL circuit
1000
, however, single delay line causes a problem that the interval of generation of the internal clock pulse int.CLKP is not uniform because of variations of characteristics of the transistors constituting the delay unit.
FIG. 38
is a timing chart representing the problem of the DLL circuit
1000
in accordance with the prior art.
Referring to
FIG. 38
, in response to the rising edge of external clock signal ext.CLK, clock signal BufCLK rises after the lapse of Ti. A delay time corresponding to the count data ADR<
0
:M−1> is added by delay circuit
120
to clock signal BufCLK.
The signal BufCLKdly represents wave

Affiliated with

Also associated with

Rating

Clock generating circuit having additional delay line... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock generating circuit having additional delay line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock generating circuit having additional delay line... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2839754