Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-03-17
2001-11-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S222000, C365S230060
Reexamination Certificate
active
06320807
ABSTRACT:
BACKGROUND
The present invention is directed to an apparatus and method for precharging a high-speed memory.
Many applications have a need for high-speed random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). Such a memory is configured in rows and columns to provide an array of memory cells. Most memories can write or read multi-bit words to or from the memory array by accessing multiple adjacent columns in the memory array simultaneously. Conventional high-speed SRAMs use relatively “narrow” words, e.g., 8 or 16 bits. However, some applications have a need for high-speed memory that can access very wide words, e.g., 128 bits or more. For example, digital signal processors for communications applications need wide words in order to load a full packet of data into a processor module. As another example, high-powered word processing programs with long instructions may need to access data with very wide words.
Unfortunately, wide-word high-speed SRAMs can bum a large amount of power. Specifically, in an SRAM, one bit line for each memory cells being accessed needs to be discharged during each read operation. Since the wide-word SRAMs access a large number of columns simultaneously, a large number of bit lines need to be precharged and discharged for each read operation. Moreover, since the SRAM is operating at high speed, the memory array is being accessed for read operations at high frequencies, and the bit lines need to be precharged and discharged frequently. Due to the frequent read operations and the large number of bit lines that need to be precharged and discharged for each read operation, a conventional high-speed wide-word SRAM can consume a large amount of power. High power consumption can make a chip unsuitable for many battery-powered devices.
One prior art technique to reduce power consumption in SRAMs is to divide the memory array into multiple sections by columns and/or rows. Each section of the memory array is independently prechargeable. During a read operation, only the section of the memory being accessed is precharged. The remaining sections of the memory remain are left uncharged. Unfortunately, breaking the memory array into multiple independently prechargeable sections requires a large number of independent precharge lines and control gates and a large number of sense amplifiers. This increases the physical size (i.e., the required area on the chip) of the memory. In addition, the precharge lines, gates and sense amplifiers require a large number of interconnects, which may not be physically available on the chip.
SUMMARY
In one aspect, the invention is directed to a random access memory device. The memory device has a memory array, a precharge line, at least one pass device, and a control logic. The memory array has a plurality of columns, with each column including a plurality of memory cells and a first bitline. The precharge line connects the first bitline to a voltage source to precharge at least a portion of the memory cells in the column before a read operation. The pass device is connected to the first bitline and divides the memory cells into a first section on one side of the pass device and a second section on an opposite side of the pass device. The control logic opens the pass device during the read operation if a memory cell in the first section is accessed so that memory cells in the first section are discharged and memory cells in the second section are not discharged during the read operation, and closes the pass device during the read operation if a memory cell in the second section is accessed so that memory cells in both the first and second sections are discharged during the read operation.
Implementations of the invention may include one or more of the following features. The first section may be located on a side of the pass device nearer the precharge line, and the second section may be located on a side of the pass device farther from the precharge line. The precharge line may be electrically connected to a bottom of the column. The first section may be located below the pass device, and the second section may be located above the pass device. Output lines may be electrically coupled to the first bitline from each column. The first section may be located on a side of the pass device nearer the output line, and the second section may be located on a side of the pass device farther from the output line. The output lines may be electrically connected to the bottom of the columns. The pass device may be closed during precharging. Each column may have a second bitline, and a sense amplifier may be coupled to the first and second bitlines.
In another aspect, the invention may be directed to a random access memory device with a memory array having a plurality of columns. Each column includes a plurality of memory cells and a first bitline. A precharge line connects the first bitline of each column to a voltage source to precharge at least a portion of the memory cells in the column before a read operation. In each column, a plurality of N pass devices are connected to the first bitline. The pass devices dividing the memory cells into N+1 sections. There are a plurality of output lines, each output line electrically connected to an end of one of the first bit lines from one of the columns. A control logic opens the pass devices on a side of a section being accessed farther from the output lines during the read operation and closes the pass devices on a side of the section being accessed closer to the output lines during the read operation.
In another aspect, the invention is directed to a method of operating a random access memory device. In the method, at least a portion of a plurality of memory cells in a column of a memory array are precharged by connecting a bitline in the column to a voltage source. A pass device connected to the bit line divides the memory cells into a first section and a second section. An address of one of the plurality of memory cells to be accessed is determined for a read operation. The pass device is closed if a memory cell in the first section is to be accessed and opened if a memory cell in the second section is to be accessed. Then the memory cell is read.
In another aspect, the invention is directed to a random access memory device. The memory device has a memory array with a plurality of columns. Each column includes a plurality of memory cells and a bitline. A precharge line connects the bitlines to a voltage source to precharge at least a portion of the memory cells in the column before a read operation. At least one pass device is connected to the bitlines. The pass device divides the memory cells into a first section on a side of the pass device nearer the precharge line and a second section on a side of the pass device opposite the precharge line. A control logic opens the pass device during the read operation if a memory cell in the first section is to be accessed during the read operation so that the memory cells in the first section are precharged, and closes the pass device during precharging if a memory cell in the second section is to be accessed during the read operation so that the memory cells in the first and second sections are precharged.
Implementations of the invention may include the following features. The precharge line may be electrically connected to a bottom of the column. The first section may be located below the pass device, and the second section may be located above the pass device.
Potential advantages of implementations of the invention can include zero or more of the following. Power consumption in a high-speed wide-word memory, such as an SRAM, can be reduced, without significantly increasing the physical size of the memory. A controllable portion of a memory array in the SRAM can be precharged using a simple precharge control logic.
Other features and advantages of the invention will become apparent from the following description, which includes the drawings and the claims.
REFERENCES:
patent: 5751651 (1998-0
Fish & Richardson P.C.
Le Vu A.
Nguyen Hien
RealChip, Inc.
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