Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-01-28
2004-12-07
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S222000, C365S204000, C365S191000
Reexamination Certificate
active
06829184
ABSTRACT:
BACKGROUND OF THE INVENTION
In the area of memories, dynamic random access memories (DRAMs) typically perform as the main memory of a computer system. That is, in a typical computer system, such as a desk top personal computer (PC), the main memory function is performed by DRAM devices. The operation of a DRAM generally entails the use of row and column addresses for addressing the memory, so that read and write operations may be performed on the DRAM components. It is appreciated that in many instances, DRAMs are utilized with a processor, such as a central processing unit of a computer, but in other instances, the DRAM may be used with other processing/controlling devices, such as memory controllers.
In order to provide much higher performance in faster computer systems, higher performance requirements are also placed on DRAMs to process data in much larger quantities and in much faster performance time. Thus, it is not uncommon to find DRAMs configured into banks of DRAM arrays, in which data transfer to and from the DRAM arrays are achieved by high data speed bursts. For example, a high-speed 256 mega bit (Mb) DRAM, arranged in multiple banks, may be clocked to provided data transfer with an issuance of a read and/or write access command. In one such configuration, it may be possible to provide a specialized clocked signal (referred to as a flag signal) to trigger the data transfer in response to the read or write access to the DRAM. In some instances, the data transfer may be effected with both the rising and falling transitions of the flag signal. For example, a first read/write access may be triggered on a rising transition of such a flag signal, while a second read/write access may be triggered in response to the falling transition of the flag signal. This data transfer to/from the DRAM at both the rising and falling transitions of the flag signal may allow two memory accesses in response to one cycle of the flag signal. For example, such a scheme may be implemented so that data transfer to/from one portion of the memory may be achieved in response to the rising transition of the flag signal and a second data transfer occurs to/from another portion of the memory in response to the falling transition of the clock signal.
It is also generally understood that DRAM devices utilize a precharge function. Precharging a DRAM generally refers to an operation that charges the bit lines to a pre-selected value. An auto-precharge condition automatically precharges the bit lines in response to an issuance of a command, such as a read or write command. That is, in some instances a read or write command may initiate an auto-precharge of the accessed bit lines prior to performing the read or the write function. With most DRAMs, the precharge or auto-precharge function typically has a signal sent from a processor or controller to the DRAM device in order to perform the precharging operation. The command generally requires a specialized pin on the DRAM device to receive the precharge command. It is appreciated that if the precharging (or auto-precharging) is encoded with another signal being transmitted to the DRAM, then a designated pin need not be utilized for designating the precharge condition. This results in reduced pin count for the DRAM device, or alternatively the extra pin designated previously for the precharge/auto-precharge function may now be utilized for other signals being sent or received from the DRAM.
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Khandekar Narendra S.
Williams Michael W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Viet Q.
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