Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1998-02-11
2001-09-18
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C365S202000, C365S190000, C365S207000
Reexamination Certificate
active
06292416
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention deals with Random Access Memories (RAMs). More specifically, the present invention deals with high performance DRAMs.
2. Discussion of the Related Art
A typical Random Access Memory (RAM) includes memory array and peripheral circuits. The memory array is typically arranged in rows and columns of memory cells. Each row of the memory cells can be accessed by activating a word line. Each column of the memory cells can be accessed by addressing a bit line. The bit lines are typically provided in pairs of complementary bit lines.
In operation, the externally applied address is decoded to generate signals to assert a selected word line and a selected column. The asserted word line will cause the data stored in the memory cells within the selected row to be placed on the corresponding pairs of bit lines. Thereafter, the data on the selected pair of bit lines will be sensed and placed on an I/O line.
It is well known to one knowledgeable in the art that before reading the content a memory cell, the bit lines associated with the memory cell must be pre-charged to a certain voltage level. For example in DRAM's, the pre-charge voltage level is typically equal to one half of the supply voltage. The time to pre-charge the bit lines is referred to as the pre-charge time. This time is critical in determining the read or write cycle time. Therefore, the faster the pre-charge time, the shorter is the read or write cycle.
The speed by which a bit line is pre-charged depends on the load that must be driven by the pre-charge circuit. This load is represented by the impedance of each bit line. The impedance of the bit lines is determined by its equivalent resistance and capacitance and the capacitance of the memory cells that are connected to it. The equivalent resistance and capacitance of a bit line are directly proportional to its length. The longer is the length bit line the higher is its equivalent resistance and capacitance.
In a high capacity random access memory, the number of memory cells connected to each bit line increase. Each memory cell has a finite capacitance. Thus, an increase in the number of memory cells connected to a bit line directly increases the total capacitance connected to the bit line.
Accordingly, in a high capacity random access memory, the impedance of the bit lines increases substantially. This means that the time that it takes for the pre-charge circuit to pre-charge a bit line increases substantially. This is not acceptable in a high performance and high capacity random access memory.
Accordingly, there is a need for a high capacity and high performance random access memory with shorter pre-charge time.
OBJECTIVES AND SUMMARY OF THE INVENTION
It is the object of the present invention to provide a RAM with a shorter pre-charge time.
According to the first embodiment of the present invention, a pre-charge device is coupled to the middle of each complementary bit line. Once the pre-charge device is activated, it shorts the middle of the bit lines together causing the voltage on the bit lines to be equal to half of the aggregate voltages on the bit lines before the activation of the pre-charge device. Furthermore, the pre-charge device drives a load that is half of the load represented by the RC impedance of the entire bit lines in each direction. Thus, the bit lines are pre-charged in a much shorter time.
According to the second embodiment of the present invention, a first pre-charge device is coupled to one end of each complementary bit line and a second pre-charge device is coupled to approximately the middle of each complementary bit line. Once both devices are activated, the bit lines are shorted together in two locations, at one end and in the middle. The shorting of the two bit lines causes the voltage on each bit line to a level equal to the half of the aggregate voltages of the two bit lines before the activation of the pre-charge devices. Furthermore, each pre-charge device drives a load equal to half of a load represented by the RC impedance of the entire bit lines. Thus, the pre-charge time is substantially reduced
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Kengeri Subramani
Reddy Chitranjan N.
Alliance Semiconductor Corporation
Beyer Weaver & Thomas LLP
Nguyen Viet Q.
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