Active refresh circuit for dynamic MOS circuits

Static information storage and retrieval – Read/write circuit – Precharge

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3072383, 365222, G11C 1140

Patent

active

042913934

ABSTRACT:
Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at an intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor connected between the drain supply and a digit line having a gate connected to the source of a second transistor. The drain of the second transistor is connected to a clocked source of potential at least one threshold above the drain supply. The gate of the second transistor is precharged to a potential near the drain supply voltage preferrably concurrent with precharging of digit lines in the memory proper. A third transistor is connected between the gate of the second transistor and the digit line and has a gate connected to a clocked source of a reference potential between a digit line precharge level and the level of one threshold above ground. After the state of a memory cell is read out by a sense amplifier, the reference potential is applied to the gate of the third transistor to discharge the gate of the second transistor in the event that the digit line is at a low voltage. If the cell read out on the digit line was at a high potential the gate of the second transistor remains charged so that when a potential exceeding the drain voltage by at least one threshold is applied to the drain of the second transistor it is coupled through to the gate of the first transistor which in turn pulls the digit line potential to the drain supply voltage.

REFERENCES:
patent: 3942162 (1976-03-01), Buchanan
patent: 4028557 (1977-06-01), Wilson
patent: 4061999 (1977-12-01), Proebsting
patent: 4091360 (1978-05-01), Lynch

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