Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2005-07-26
2005-07-26
Yoha, Connie C. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Precharge
C365S202000, C365S226000, C365S227000, C365S228000, C365S229000
Reexamination Certificate
active
06922368
ABSTRACT:
A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.
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Schwegman Lundberg Woessner & Kluth P.A.
Yoha Connie C.
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