Apparatus for and method of current leakage reduction in...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S204000, C365S154000

Reexamination Certificate

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07852693

ABSTRACT:
A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array includes memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged.

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Sharifkhanir et al., “A Low Power SRAM Architecture Based on Segmented Virtual Grounding”, <http://delivery.acm.org/10.1145/1170000/1165635/p256-sharifkhani.pdf?key1=1165635&key2=4126760711&coll=&dl=acm&DFID=15151515&CFT>.
Kanda et al., “Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAMs by Row-by-Row Dynamic Vdd Control (RRDV) Scheme”, Proceedings 15th Annual IEEE International ASIC/SOC Conference (Cat. No. 02TH8626), 2002, pp. 381-385.
Romanovsky et al., “Leakage Reduction Techniques in a 0.13 UM SRAM Cell”, Proceedings. 17th International Conference on VLSI Design, 2004, pp. 215-221.
Aly et al., Precharged SRAM Cell for Ultra Low-Power On-Chip Cache, Proceedings IEEE International SOC Conference, Proceedings—IEEE International SOC Conference, 2005 SOCC, 2005, pp. 95-98.

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