Address decoding

Details Address decoding Address decoding

2007-08-28

2007-08-28

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230060, C365S233100

Reexamination Certificate

active

11267574

ABSTRACT:
A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.

REFERENCES:
patent: 5699309 (1997-12-01), Cronin et al.
patent: 6269045 (2001-07-01), Durham et al.
patent: 6501695 (2002-12-01), Brown
patent: 6621758 (2003-09-01), Cheung et al.
patent: 7064992 (2006-06-01), Bell et al.
patent: 7085190 (2006-08-01), Worley et al.

Affiliated with

Also associated with

Rating

Address decoding does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address decoding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address decoding will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3853418