Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-03-30
2003-08-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S196000, C365S207000, C365S244000
Reexamination Certificate
active
06608786
ABSTRACT:
FIELD OF INVENTION
The field of invention relates to semiconductor memory technology generally; and more specifically, to an apparatus and method for a memory storage cell leakage cancellation scheme.
BACKGROUND
FIG. 1
shows a prior art Random Access Memory (RAM) cell
100
. The prior art RAM cell
100
of
FIG. 1
includes a plurality of “N” storage cells S
1
through S
N
(each of which may correspond to static RAM (SRAM) cells). Each of the storage cells S
1
through S
N
stores a bit of data. Data is read from a particular storage cell by activating its corresponding word line (WL) (e.g., WL
1
for storage cell S
1
, WL
2
for S
2
, etc.). During a typical storage cell read operation, the bit lines
101
,
102
are pre-charged to a “high” voltage.
The word line of the storage cell to be read (e.g., word line WL
1
for storage cell S
1
) is activated (e.g., with a “high” voltage) while the word lines for the remaining “un read” storage cells (e.g., word lines WL
2
through WL
N
for storage cells S
2
through S
N
, respectively) are deactivated (e.g., with a “low” voltage). Upon the activation of the word line for the storage cell to be read (e.g., word line WL
1
for storage cell S
1
), the storage cell to be read drives one of the bit lines to a “low” voltage.
For example, if the data stored in storage cell S
1
corresponds to a “1”, storage cell S
1
drives bit line
102
to a “low” voltage while bit line
101
remains at the pre-charged “high” voltage. By contrast, if the data stored in storage cell S
1
corresponds to a “0”, storage cell S
1
drives bit line
101
to a “low” voltage while bit line
102
remains at the pre-charged “high” voltage.
FIG. 1
shows an example of the later case (i.e., storage cell S
1
has a “0” stored) because drive current Isc is observed being driven from bit line
101
by storage cell S
1
.
Because the voltages on the bit lines
101
,
102
during a storage cell read are different (i.e., one voltage being high, the other voltage being low), a differential signal may be said to exist on the bit lines
101
,
102
. The differential signal provided on the bit lines
101
,
102
may be expressed as:
Signal=
V
1
-V
2 Eqn.1
where V
1
is the voltage on bit line
101
and V
2
is the voltage on bit line
102
. Note that the actual high and low voltages on the bit lines may vary from embodiment to embodiment. Furthermore, note that the greater the difference between V
1
and V
2
, the greater the differential signal observed on the bit lines
101
,
102
.
Storage cell leakage may cause an increase in the amount of time it takes the differential voltage to develop on the bit lines
101
,
102
during a bit cell read. As such, the speed of operation of the RAM cell
100
may be adversely affected by the storage cell leakage. The rate at which the differential voltage is created during the course of a storage cell read, without storage cell leakage, may be expressed as:
Dv/Dt=Isc
/(
Cb
+2
Cc
) Eqn. 2
where: 1) Cb is the capacitance of the bit line being pulled down; 2) Cc is the capacitance between the bit lines
101
,
102
; and 3) Isc is the amount of drive current pulled by a storage cell being read from.
From Equation 2, it is apparent that the rate at which the differential voltage is created increases as Isc increases. Storage cell leakage has the effect of the reducing the Isc term in Equation 2 and, as such, reduces the rate at which the differential voltage is created. Storage cell leakage is the tendency of a storage cell, that is not being read from, to pull current from a bit line. As the number of “un-read” cells that pull leakage current from the “high” bit line increases, the impact on the rate at which the differential voltage worsens.
A worse case condition is exemplified in FIG.
1
. Specifically, during a read of storage cell S
1
which pulls current Isc from the low bit line
101
, each of the remaining N−1 storage cells (i.e., storage cells S
2
through S
N
) pull leakage current I
L
from the high bit line
102
. Each leakage current I
L
from the high bit line
102
will cause a drop in the high bit line
102
voltage. As such, N−1 leakage currents I
L
from the high bit line
102
(as seen in
FIG. 1
) corresponds to a worst case voltage drop on the high bit line
102
.
From the perspective of the differential voltage being established between the pair of bit lines
101
and
102
, as the high bit line
102
voltage drops from the N−1 leakage currents I
L
, the effect of dropping the low bit line
101
voltage with the drive current Isc is reduced. This corresponds to a decrease in the differential signal voltage which corresponds to a decrease in the rate at which the differential signal voltage is developed.
That is, for the worst case condition shown in
FIG. 1
, the rate at which the differential voltage is created during the course of a storage cell read, with storage cell leakage, may be expressed as:
Dv/Dt
=(
Isc
−(N−1)
I
L
)/(
Cb
+2
Cc
) Eqn. 3
where: 1) Cb is the capacitance of the bit line being pulled down; 2) Cc is the capacitance between the bit lines
101
,
102
; 3) Isc is the amount of drive current pulled by a storage cell being read from; and 4) (N−1)I
L
is the total amount of leakage current being pulled from the high bit line
102
. As seen in Equation 3, the leakage current term (N−1)IL subtracts from the drive current term Isc. This corresponds to a drop in the rate at which the differential voltage is developed. As discussed, this corresponds to a drop in the speed of the RAM cell
100
.
REFERENCES:
patent: 4730279 (1988-03-01), Ohtani
patent: 6049492 (2000-04-01), Vogelsang et al.
patent: 6067253 (2000-05-01), Gotou
patent: 6078523 (2000-06-01), Pascucci
patent: 6128225 (2000-10-01), Campardo et al.
patent: 6266292 (2001-07-01), Tsern et al.
patent: 6288949 (2001-09-01), Hidaka et al.
patent: 6353569 (2002-03-01), Mizuno et al.
patent: 6373745 (2002-04-01), Saito et al.
Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, and Tadahiro Kuroda, A Bit-LineLeakage Compensation Scheme for Low-Voltage SRAM's. IEEE, 2000, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 70-71.
De Vivek K.
Hamzaoglu Fatih
Somasekhar Dinesh
Ye Yibin
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