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Selected: M

Memory device having redundant memory for repairing defects

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device having selectable redundancy for high endurance an

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device having shared fail-repairing circuit capable...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device having valid bit storage units to be reset in batc

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device including redundancy cells with programmable fuel

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device redundancy selection having test inputs

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device to detect and compensate for defective memory cell

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with address translation for skipping failed...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device with built-in error-correction capabilities

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device with clocked column redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with common row interface

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory device with efficient redundancy using sense amplifiers

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with global redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with multiple-bit data pre-fetch function

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with reduced number of fuses

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory device with redundancy arrays

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory devices having a flexible redundant block architecture

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory employing multiple enable/disable modes for redundant...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory having and method for testing redundant memory cells

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory having error detection and correction

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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