Memory device including redundancy cells with programmable fuel

Details Memory device including redundancy cells with programmable fuel Memory device including redundancy cells with programmable fuel

1990-08-13

1993-10-26

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, 365104, 365178, 3652257, G11C 1716

Patent

active

052572307

ABSTRACT:
There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

REFERENCES:
patent: 4230504 (1980-10-01), Kuo
patent: 4333164 (1982-06-01), Orikabe et al.
patent: 4541074 (1985-09-01), Nultano
patent: 4970686 (1990-11-01), Naruke et al.
patent: 4985866 (1991-01-01), Nakaizumi
Naruke et al., A 16Mb Mask ROM with Programmable Redundancy, IEEE Int'l. Solid State Circuits Conf., Feb. 16, 1989, pp. 128-129.

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