Memory device with reduced number of fuses

Details Memory device with reduced number of fuses Memory device with reduced number of fuses

1995-10-31

1997-07-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, 36523003, 36523005, G11C 700

Patent

active

056468962

ABSTRACT:
A redundancy circuit for a multiport memory device with first and second memories includes a fuse programming circuit, shared between the first and second memories, for programming a first redundant address. A first address compare circuit compares a received address for the first memory with the first redundant address. The first address compare circuit generates a redundant address selection signal when the received address is the same as the first redundant address. A second address compare circuit compares a second received address for the second memory with the first redundant address. The second address compare circuit generates a redundant address selection signal when the received address is the same as the first redundant address.

REFERENCES:
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 4961171 (1990-10-01), Pinkham et al.
patent: 5313423 (1994-05-01), Sato et al.
Pinkham et al., "A 128K.times.8 70-MHz Multiport Video RAM with Auto Register Reload and 8.times.4 Block Write Feature," IEEE Journal of Solid-State Circuits, 23:1133-1139 (Oct., 1988).

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