Memory device with redundancy arrays

Details Memory device with redundancy arrays Memory device with redundancy arrays

2000-05-10

2001-02-20

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230040, C365S230030

Reexamination Certificate

active

06191986

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory device with redundancy arrays. More particularly, it relates to a memory device which uses the different logic values of several particular row address signals to drive either odd arrays or even arrays of the different blocks in the same bank, so that defective rows and normal rows located in different blocks of the memory device don't have to be replaced by spare rows at the same time.
DESCRIPTION OF THE PRIOR ART
High-density memory such as dynamic random access memory arrays rely on the design of redundancy arrays to improve yields by repairing defective memory devices. Redundancy arrays generally include spare columns and spare rows. A traditional memory device with sense-sharing amplifiers SA and spare rows is shown in
FIG. 1A. A
plurality of row address signals, for example A
0
-A
9
, received by a memory device are decoded by the row decoders to select a corresponding row word line. Generally, a memory device is divided into a plurality of banks. Take bank
1
for example. The bank selective signal BK
1
is used to select bank
1
; In addition, bank
1
is further divided into two blocks such as the first block
1
A and the second block
1
B; each block includes 2
n
(n≧0, n is an integer) memory arrays, spare rows that correspond to the memory arrays, and 2
n
+1 sense-sharing amplifiers SA. In case of two memory arrays MA
1
,MA
2
, the corresponding spare rows SR
1
(4), SR
2
(4) separately offer 4 spare rows for replacement.
When the row decoders XDEC
1
-
2
decode row address signals A
0
-A
9
and address a normal row word line, the enable signal en will enable the row decoder, one of XDEC
1
-
2
, for example XDEC
1
, in order to drive the normal row word line like WL
1
; if the row decoders XDEC
1
-
2
decode row address signals A
0
-A
9
and address a defective row word line, the row replace signal spr will enable one of the spare row decoders SX
1
-
2
, for example SX
1
, in order to drive one of the four spare rows SR
1
(4), which will replace the defective row.
The problem with this system is that if the row WL
1
is defective only in the first block
1
A, not only the first block
1
A but also the normal row in the second block
1
B will be replaced. That is, the repair rate for redundancy arrays is only half.
Further, a traditional memory device with sense-sharing amplifiers SA and spare columns, as shown in
FIG. 1B
, is generally divided into 2
n
(n≧0, n is an integer)memory arrays, and 2
n
+1 sense-sharing amplifiers SA. Take
4
memory arrays MA
5
-
8
for example. The column decoder YDEC decodes column address signals in order to select a column selective line CSL, wherein the column selective elements located in the sense-sharing amplifiers SA are all driven at the same time. Therefore, if the column selective line in the particular arrays like MA
5
, MA
7
is a defective column and replaced by one of the spare columns SC, the normal columns addressed by the same column address signals in the memory arrays MA
5
-
8
will be replaced by the spare columns SC at the same time. Therefore, the repair rate for the redundancy arrays is only half.
SUMMARY OF THE INVENTION
The present invention provides a memory device with redundancy arrays, which comprises row word lines and column selective lines respectively selected by a plurality of row address signals and column address signals. A bank has a first block and a second block, wherein the first block and the second block are separately driven by the different logic values of the first row address signal. In addition, a plurality of pairs of odd arrays and even arrays and a plurality of spare rows and spare columns corresponding to the odd arrays and the even arrays are located in the first blocks and the second blocks. The odd arrays and the even arrays are separately driven by the different logic values of the second row address signal. The other row address signals are used to select the row word lines located in the odd arrays or the even arrays. When the selected row word line is a defective row, it will be replaced by one of the spare rows; when the column selective line selected by a plurality of column address signals is a defective column, it will be replaced by one of the spare columns.
Since the first blocks and the second blocks are separately driven by the different logic values of the first row address signal, spare rows won't be used to replace the normal rows and the defective rows in the first blocks and in the second blocks at the same time. Therefore, the repair rate for the redundancy arrays is doubled.
In addition, since the odd arrays and the even arrays are separately driven by different logic values of the second row address signal, spare columns won't be used to replace the normal columns and the defective columns of the odd arrays and the even arrays at the same time. Therefore, the repair rate for the redundancy arrays is doubled.


REFERENCES:
patent: 5303192 (1994-04-01), Baba
patent: 5835424 (1998-11-01), Kikukawa

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