Memory device having redundant memory for repairing defects

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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Details

C365S230030, C365S063000

Reexamination Certificate

active

11227038

ABSTRACT:
First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic of a second memory chip. The second memory chip has a control logic for effecting memory control of the memory cells, the redundant memory cells, etc. and a redundant memory cell for repairing an error bit of the first memory chips. The memory device is structured by stacking the first and second memory chips.

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patent: 5796662 (1998-08-01), Kalter et al.
patent: 6324114 (2001-11-01), Himeno
patent: 6674673 (2004-01-01), Hsu et al.
patent: 6674676 (2004-01-01), Hsu et al.
patent: 2004-071104 (2004-03-01), None
patent: 2004-087100 (2004-03-01), None
patent: 2004-264057 (2004-09-01), None
patent: 2005-100517 (2005-04-01), None

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