Memory device with clocked column redundancy

Details Memory device with clocked column redundancy Memory device with clocked column redundancy

1997-06-03

1998-11-03

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

36518902, G11C 700

Patent

active

058319158

ABSTRACT:
A semiconductor memory device including: at least one output data terminal; a matrix of memory cells having a plurality of columns of memory cells; multiplexer circuitry associated with the matrix of memory cells for selectively coupling one of the columns to respective sensing circuitry driving the output data terminal; redundancy columns of redundancy memory cells for functionally replacing defective columns in the matrix; first registers for storing defective addresses of the defective columns in the matrix, for comparing the defective addresses with a current address supplied to the memory device and for selecting a redundancy column when the current address coincides with one of the defective addresses; circuitry for generating an internal timing signal activated upon changing of a current address supplied to the memory device, the internal timing signal remaining activated for a prescribed time starting from the beginning of a read cycle of the memory device. The memory device includes: redundancy sensing circuitry associated with the redundancy columns, and redundancy control circuitry controlled by the internal timing signal for coupling the output data terminal of the memory device to the redundancy sensing circuitry in alternative to the sensing circuitry when the current address supplied to the memory device is a defective address, the redundancy control circuitry maintaining the output data terminal of the memory device coupled to the sensing means independently of the current address being a defective address as long as the internal timing signal is activated.

REFERENCES:
patent: 4811298 (1989-03-01), Helwig et al.
patent: 5708601 (1998-01-01), McKenny et al.

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