Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-06-24
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06188619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor memory device capable of operating normally even when a failed memory cell exists after repair.
2. Description of the Related Art
A semiconductor memory device includes a plurality of memory cells which must be function properly in order for the memory device to function properly. However, during manufacture of the memory device, some of the memory cells may be defective. To solve this problem, semiconductor memory devices include redundant memory cells capable of being used in place of such failed memory cells. When failed memory cells are detected, the failed memory cells are replaced by the redundant memory cells to “repair” the memory device. This procedure improves the manufacturing yield, reducing the cost of manufacture of the memory devices.
However, if the number of failed memory cells is greater than the number of redundant memory cells capable of replacing the failed memory cells, the semiconductor memory device will not function properly. Thus, if any failed memory cells remain after the repair process, the semiconductor memory device is considered to be defective.
SUMMARY OF THE INVENTION
To solve the above problem, the present invention provides a semiconductor memory device capable of operating normally even when failed memory cells exist after the repair process.
Accordingly, there is provided a semiconductor memory device comprising a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective, and address decoding circuitry for receiving an address and for accessing the memory cell array blocks having only good memory cells and skipping the memory cell array blocks having at least one defective memory cell. The address decoder preferably receives at least one selection signal indicating which memory cell array blocks have only good memory cells and which memory cell array blocks have at least one defective memory cell, and preferably includes a plurality of fuses for designating which memory cell array blocks have only good memory cells and which memory cell array blocks have at least one defective memory cell, the fuses being adapted to be cut, and wherein the selection signal is generated according to which fuses are cut.
In accordance with another aspect of the invention there is provided a semiconductor memory device comprising a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective, and address decoding circuitry for receiving a first address, decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address, and generating a plurality of internal address signals, the internal address signals corresponding to a second address. If the memory device has no memory cell array block having at least one defective memory cell, the second address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the second address is different from the first address.
In accordance with yet another aspect of the invention there is provided a method for addressing a plurality of memory cell array blocks in a memory device, comprising determining which memory cell array blocks of the plurality of memory cell array blocks have at least one defective memory cell, receiving a first address providing for access to one of the memory cell array blocks, decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address, and generating a plurality of internal address signals, the internal address signals corresponding to a second address. If the memory device has no memory cell array block having at least one defective memory cell, the second address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the second address is different from the first address.
REFERENCES:
patent: 5506807 (1996-04-01), Ferrant et al.
patent: 5671184 (1997-09-01), Meyer
patent: 5691945 (1997-11-01), Liou et al.
patent: 5808944 (1998-09-01), Yoshitake et al.
Lam David
Lee, Esq. Eugene M.
Nelms David
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee P.L.L.C.
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