Memory device having valid bit storage units to be reset in batc

Details Memory device having valid bit storage units to be reset in batc Memory device having valid bit storage units to be reset in batc

1987-06-08

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 365218, 36518901, 365 49, G11C 700, G11C 1140

Patent

active

048796875

ABSTRACT:
A memory device includes plural word data storing rows. Each word data storing row is composed of a plurality of data bit cells for storing the word data, and a valid bit cell for indicating the validity of data. The valid bit cell has a reset circuit composed of FETs, and the reset circuits are connected to one reset line. By applying a reset signal to one reset line, plural valid bit cells are reset as a batch.

REFERENCES:
patent: 4244033 (1981-01-01), Hattori
patent: 4390946 (1983-06-01), Lane
patent: 4689772 (1987-08-01), Jordy

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