Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1996-11-21
1998-06-02
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 36518908, 3652257, G11C 700, G11C 800
Patent
active
057611386
ABSTRACT:
A memory device includes a plurality of data input/output (I/O) lines and means for receiving a column address. The memory device also includes a plurality of primary memory cells, a selected primary memory cell of the plurality of primary memory cells being connected to a primary global I/O line in response to receipt of one column address, and a plurality of redundant memory cells, a selected redundant memory cell of the plurality of redundant memory cells being connected to a redundant global I/O line in response to receipt of the one column address. One of the primary global I/O line and the redundant global I/O line are selectively connected to one of the plurality of data I/O lines such that one of the selected primary memory cell and the selected redundant memory cell is connected to the one data I/O line to thereby enable data transfer therebetween, preferably by enabling one of a primary I/O sense amplifier and a redundant I/O sense amplifier connected to the primary and redundant global I/O lines, respectively.
REFERENCES:
patent: 4807191 (1989-02-01), Flannagan
patent: 5045720 (1991-09-01), Bae
Kim Keum-Yong
Lee Kyu-Chan
Nelms David C.
Phan Trong
Samsung Electronics Co,. Ltd.
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