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Power savings for memory arrays

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pre-emphasis for strobe signals in memory device

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Precharge control signal generator, and semiconductor memory...

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable delay compensation circuit

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Programmable delay for self-timed-margin

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Programmable high speed array clock generator circuit for array

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable memory array control signals

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable mode register for use in synchronized memory device

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable self time circuitry for memories

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Programmable semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking
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Programmable stackable memory array system

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Protection circuit to ensure DRAM signal in write cycle

Static information storage and retrieval – Addressing – Sync/clocking
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Pseudo SRAM having combined synchronous and asynchronous...

Static information storage and retrieval – Addressing – Sync/clocking
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Pseudo SRAM with common pad for address pin and data pin

Static information storage and retrieval – Addressing – Sync/clocking
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Pseudo static random access memory employing dynamic memory cell

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pseudo-dual port memory where ratio of first to second...

Static information storage and retrieval – Addressing – Sync/clocking
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Pseudo-static synchronous semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking
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Pulse driver

Static information storage and retrieval – Addressing – Sync/clocking
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Pulse generation circuit and memory circuit including same

Static information storage and retrieval – Addressing – Sync/clocking
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