Static information storage and retrieval – Addressing – Sync/clocking
Patent
1987-11-13
1989-10-03
Moffitt, James W.
Static information storage and retrieval
Addressing
Sync/clocking
365194, 365195, G11C 800
Patent
active
048721433
ABSTRACT:
A pseudo static RAM includes an array of dynamic memory cells and peripheral circuits such as precharge transistors, a row decoder and sense amplifiers. Address change detecting circuits detect address signal change. A pulse generator supplies a pulse signal to a timing generator and a busy signal generator in response to the address signal change. The timing generator generates various timing signals for driving the peripheral circuits. When a subsequent address signal change is detected during operation of a dynamic RAM, a flag circuit generates a flag signal in response to a subsequent pulse signal from the pulse generator and a busy signal from the busy signal generator. Thus, the signal commanding such subsequent operation of the pseudo static RAM is stored in the form of a flag signal until the first operation is completed. Upon completion of first operation of the dynamic RAM, subsequent operation is started on the basis of the flag signal.
REFERENCES:
patent: 4581718 (1986-04-01), Oishi
patent: 4660180 (1987-04-01), Tanimura et al.
ISSCC, 1986 IEEE, "Session XVII: Logic Arrays and Memories", by Takayuki Sakurai et al, Feb. 21, 1986, pp. 252-253.
Mitsubishi Denki & Kabushiki Kaisha
Moffitt James W.
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