Programmable high speed array clock generator circuit for array

Details Programmable high speed array clock generator circuit for array Programmable high speed array clock generator circuit for array

1994-06-08

1995-01-31

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36518901, 327292, 327295, G11C 1130

Patent

active

053863925

ABSTRACT:
An integrated circuit incorporating at least a SRAM that includes memory, a data-out shift register, an ABIST data compression circuit, a fail address register and an array clock generator (ACG), the ACG comprising a clock chopper that comprises a first AND gate having an inherent delay DEL1, a first input for receiving a D clock signal, a second input for receiving the D signal inverted by an invertor having an inherent delay DEL2, and an output that generates an ungated LSSSD C clock signal; and a second AND gate having an inherent delay DEL4, a first input connected to the output of an inverter having an inherent delay DEL3, the inverter is coupled to the invertor having the delay DEL2, a second input is controlled by the D clock signal and an output for generating LSSD clock signals B and S.

REFERENCES:
patent: 4692633 (1987-09-01), Ngai et al.
patent: 5172010 (1992-12-01), Montegari
patent: 5327394 (1994-07-01), Green et al.

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